edakit documentation

SIM

The scenarios run, are complete and reach the states they expect – 6 codes.

Each engine decides one kind of relation; a finding's code is ENGINE.relation. Severities are the catalog's defaults – a project's domains may set others; a grade is a sub-case with its own severity, a topic the part of a code a domain switches on.

SIM.config simulation config readable

erroroff: note

The simulation config names existing parts, nets and boards, and every value has the form the config needs; a part whose thresholds are ratios has one supply pin to take them of.

Why
A config the simulation cannot read checks nothing.
What to do
Correct sim.json as the message says.
Sources
  1. edakit handbook 5.1

Replaces E-1, E-3

SIM.converge every scenario converges

error

The operating point of every scenario converges, every transient run reaches its end.

  • the operating point converges, a transient run runs to its end; a net of copper that stays one node is noted (info) with the reason
Why
A scenario that does not converge checks nothing. Usually a node has no DC path to ground or a parameter is missing.
What to do
Give a floating node a path (often a real design fault), or complete the parts entry.
Sources
  1. edakit handbook 5.1

Replaces E-1

SIM.state the circuit does what the scenario expects

errorcc: warning

In every scenario the circuit reaches the state its load expects: LEDs on or dark, each LED of a driver channel at its share of the set current and parallel LEDs sharing it, a regulator's output at its set voltage, a blocking diode blocking, the board drawing at least a supply's minimum load, an LED the right way round, each LED in the string of a constant-current LED driver at its share of the set current or dark while the driver's dim pin is low (grade cc), and what the project plugin checks. A boost converter its enable switches off has no set voltage to reach: its output – what its inductor and diode pass from the input – is a row of information, and what hangs on it is judged at that level.

  • function: current from every source (≤ i_max_a; ≥ i_min_a with every MCU at its i_core_min_a – 5.1), no source and no cell fed backwards (≤ i_back_max_a, i_charge_max_a, 1 mA by default), regulator outputs within tolerance, input above vin_min_v, LDO junction temperature – an MCU module's own LDO too, with the core current it carries (5.3) – against the same limit as LIM.t's, MCU supply voltage and load on its regulator, MCU inputs at a defined level (≤ VIL or ≥ VIH – a 3.3 V signal into a 5 V AVR is the classic case), every part with an operating supply range inside it, every input pin with thresholds at a defined level and the high level of every MCU output reaching the VIH of the inputs on its net (5.3), MCU outputs only on pins that can drive (an output on an input-only pin is reported and not driven), LED driver output headroom and junction temperature, every LED on or dark as the load says (driver channels: ≥ 80 % of its share of the set current, also for an LED behind 0 Ω bridges or one resistor; parallel LEDs share within a ratio – 5.3), relays pull in (v_operate_v) and release (v_release_v) as the load says, an own board supplied inside the range it was simulated for (vin_min_v … vin_max_v, 4.5), diodes that must block (expect_blocking), every net inside its declared range v (a net of copper: its lowest and highest pin), plus the plugin's checks
Why
A circuit can stay within every rating and still not work. The simulation is the polarity check of the graph: a reversed LED stays dark where it should light.
What to do
Depends on the item; the protocol gives the actual and the expected value per scenario.
Sources
  1. China Resources Powtech PT4115 data sheet PT4115_DS Rev EN_2.9, p. 3 mean current sense threshold A type 95 / 98 / 101 mV, p. 4 continuous SW current 1.2 A, p. 11 'IOUT = 0.1 / Rs (Rs ≥ 0.082Ω)', p. 12–13 on-time equation TON = L × ΔI / (VIN − VLED − Iavg × (Rs + rL + Rsw)), Rsw 0.6 Ω nominal, ΔI internally 0.3 × Iavg – LCSC's copy for C84512, https://datasheet.lcsc.com/datasheet/pdf/710aeebb569349bc814ba1f6ba8cbef1.pdf (grade cc)
  2. Diodes Incorporated AL8860 data sheet DS39014 Rev. 8 - 2 (April 2026), p. 3 continuous output current TSOT25 1 A, p. 4 VSENSE 96 / 100 / 104 mV and maximum duty cycle 98 %, p. 11 IOUT_NOM = 0.1 / RS, p. 13 the same on-time equation, RSW 0.3 Ω nominal, ΔI internally 0.40 × ILED – https://www.diodes.com/assets/Datasheets/AL8860.pdf (grade cc)
  3. TI SLVA191A (Load Disconnect for the TPS6510x, May 2004, revised February 2017), abstract: 'Many boost converters have an external rectifier diode. The input voltage … is connected to the output voltage when the device is disabled' – https://www.ti.com/lit/an/slva191/slva191.pdf
  4. Xi'an Aerosemi MT3608 data sheet Rev1.1, p. 1 fig. 1 and p. 5 fig. 2: inductor and diode outside the IC, the only switch from SW to GND; p. 2 EN 'a low input turns it off' – LCSC's copy for C84817
  5. edakit handbook 5.3

Replaces E-3

SIM.driver every LED has a known driver

error

Every LED – each colour of an RGB LED – has a state the simulation checks in every scenario: its cathode on a driver output (directly, behind 0 Ω bridges or a balancing resistor), or the load lists it in leds_on. An LED a multiplexing driver scans (behaviour matrix_driver, pins on both its nets) has no DC state: a row of information.

  • LED has a known driver: in every scenario every LED – each colour of an RGB LED – has a state SIM.state checks, its cathode on a driver output (directly, behind 0 Ω bridges or one resistor) or the load's leds_on; an LED with neither, or one the netlist left out because its parts entry lacks a role it reads (anode, cathode and their colours, 4.1), fails as "LED without a known driver"
Why
Only an LED with an expected state is checked; without one a reversed LED passes without a word.
What to do
Give every load leds_on, or put the LED's cathode on a driver output; an LED left out needs its roles.
Sources
  1. edakit handbook 5.3: a reversed LED elsewhere stays dark where it should light – the polarity check of the graph
  2. edakit rules.json G-7 (retired): polarity is checked by the simulation

Replaces E-4

SIM.response frequency response as expected

warninggain: warningcorner: warning

Every expectation of an AC run of the simulation config (ac) holds: the gain from its input to its output at the frequencies named (grade gain), and the lower and upper −3 dB corners within their ranges (grade corner). The gain is 20·log10 |V(output) / V(source)| for 1 V AC behind the run's source_ohm or its source model – a pickup (R and L in series, C across), a piezo disc (behind its capacitance), an electret capsule (a current of 1 V / RL into its load resistor), named by a row of catalog/tables/audio_sources.toml with the maker's values or given as numbers –, a cable's capacitance per metre between its wires and its wire on ground, linearised around a DC scenario; a corner is where the gain falls 3.01 dB below its largest value in the sweep. Runs only where sim.json names an expectation, only with the domain audio or guitar on.

Why
A coupling capacitor ten times too small, a filter resistor of the wrong decade or a gain resistor swapped passes every DC check – the operating point is the same – and shows only as thin bass, a dull top or a level that clips the next stage. The DC-first simulation sees none of it; an expectation written next to the circuit (the corner the designer computed) holds it, the way a load's expected state holds the DC function.
What to do
Find the part that sets the corner or the gain (an RC: f = 1 / (2π·R·C); a non-inverting stage: 1 + Rf/Rg) and correct its value, or correct the expectation where it was wrong. A corner from the op-amp's bandwidth is not modelled (no gain-bandwidth in the model) – judge it from the datasheet.
Sources
  1. rules-at-scale.md, decision 9 (2026-10-31): AC analysis opt-in, where sim.json names an expectation, in the domains audio and guitar, warnings first; maker-coverage FT-12
  2. rules-at-scale.md, decision 20 (2026-10-31): the source models with the makers' published values (catalog/tables/audio_sources.toml, each row with its page or data sheet); a pickup whose maker gives no inductance takes the project's; maker-coverage FT-18
  3. ngspice 42 (Ubuntu package 42+ds-3build1): the control command ac dec <points per decade> <fstart> <fstop> and wrdata of mag(v(node)), as edakit runs them (tests/test_sim_ac.py); the manual on ngspice.sourceforge.io was not reachable from the environment where this was built

SIM.copper copper annotated

note

A net listed for copper is simulated with its routed copper; where it is not, it stays one ideal node.

Why
Information: the voltage drop along that net is not in the results.
What to do
Route the net, or take it off the list.
Sources
  1. edakit handbook 5.1

Replaces E-1