edakit documentation

ESPurna-H

Why: the only board here with mains on it – an HLK-PM01 behind a thermal fuse, a 500 mA fuse and a varistor, a 10 A relay that switches the load, and an HLW8012 power monitor on a 1 mΩ shunt and a 5 × 470 kΩ divider from neutral, whose 0 Ω resistor ties the low-voltage ground to the line. No reference circuit (tests/reference.py has none with mains or a relay) and no other open design brings LIM.hazardous and the domain mains onto a real board, nor a relay coil driven from a 3.3 V GPIO with its flyback diode; around them sit the low-voltage checks edakit does make – the 2N7002's gate drive, the regulator, the ESP8266's levels and boot pins. An HLK-PM01, an ESP module and a relay is the common recipe of a homemade mains smart switch, and ESPurna is a widely used open firmware for such switches, so a false alarm here would meet many.

Xose Pérez (tinkerman.cat), ESPurna-H, an ESP8266 wall switch with an HLK-PM01 and a power monitor, https://github.com/xoseperez/espurna-board at commit f433874 (f43387465bcd7fee6e2e6ac7c699a5177faa2fcc, 2018-04-16), the Eagle schematic espurna-h/v0.8/espurna-h.sch (title block "ESPURNA-H", version 0.8.20171028; the same file as espurna-h/espurna-h.sch), read on 2026-11-03 from a read-only clone. The bill of materials is the repository's README. The netlist was resolved from the schematic's XML by a reader outside this repository and checked against the board file espurna-h/v0.8/espurna-h.brd: all 142 pads of the schematic's 39 nets are on the same signals there. · SVG

ESPurna-H espurna-h · board main graph v1.0 (2026-11-03) · 345 x 519 mm drawn by edakit schematic draw – change the graph, not this drawing U$1 HLK-PM01 IC2 ESP-12F ADC (2) and GPIO16 (4) each on a net label of the schematic (A0, GPIO16) that nothing else is on; the Eagle package ESP-12-SMD has the 16 edge pads only, the six flash pads underneath (17–22 of the LCSC symbol) are on no net IC1 AMS1117-3.3: 5V to 3V3 the Eagle device REG1117 SOT223-2 puts VOUT on the tab (pad 4); pad 2 – VOUT inside the part – is on no net of the schematic or the board IC4 HLW8012 power monitor CF and CF1 are 50 % square waves; the simulation holds them high, the level the dividers R45/R46 and R47/R48 must bring down to the ESP's inputs JP2 KF301-5.0-2P JP21 PZ254V-11-05P JP22 PZ254V-11-05P JP42 mains terminal: 1 NO, 2 NC RLY1 SRD-05VDC-SL-C Other RESET RESET CH_PD GPIO14 GPIO14 GPIO12 GPIO12 GPIO13 GPIO13 GPIO15 GPIO2 GPIO2 GPIO0 GPIO0 GPIO4 GPIO4 GPIO5 GPIO5 RXD RXD TXD TXD V1P LINE_I LINE_I FUSE_MID LINE_L LINE_L LINE_L V1N V2P V2P_D4 V2P_D3 V2P_D2 V2P_D1 CF CF1 SEL LED Q2_D Q2_G NC NC NO NO RLY_COIL Q3_G LINE_P NEUTRAL 5V 3V3 3V3 3V3 5V 3V3 5V LINE_P NEUTRAL 5V NEUTRAL NEUTRAL 5V 3V3 3V3 3V3 5V 3V3 5V 5V NEUTRAL LINE_P AC 1 AC 2 +VO 4 -VO 3 U$1 HLK-PM01 RST 1 EN 3 GPIO14 5 GPIO12 6 GPIO13 7 VCC 8 GND 9 GPIO15 10 GPIO2 11 TXD0 16 RXD0 15 GPIO5 14 GPIO4 13 GPIO0 12 IC2 ESP-12F(ESP8266MOD) C22 100nF R26 10k RESET R21 10k + C12 10uF C21 100nF R25 10k GND 1 VOUT 4 VIN 3 IC1 AMS1117-3.3 + C11 10uF C43 100nF C44 1uF VDD 1 V1P 2 V1N 3 V2P 4 SEL 8 CF1 7 CF 6 GND 5 IC4 HLW8012 C41 33nF R43 1k F1 F2 0217.500MXP R41 0.001R C42 33nF R44 1k R42 0R C45 100nF R50 1k R55 470k R54 470k R53 470k R52 470k R51 470k R47 10k R48 15k R45 10k R46 15k 1 3 2 Q4 2N7002 R49 10k 1 2 JP2 KF301-5.0-2P 1 2 3 4 5 JP21 PZ254V-11-05P R23 10k 1 2 3 4 5 JP22 PZ254V-11-05P R22 10k 1 3 2 Q2 2N7002 R28 300 R27 22 R24 10k 1 2 3 JP42 KF301-5.0-3P 1 4 2 3 5 RLY1 SRD-05VDC-SL-C D3 LL4148-GS08 1 3 2 Q3 2N7002 R31 1k R32 10k 1 2 V11 B72210S0251K101
StageCodeWhereJudgedWhy
checkDOCS.fileedakit.tomlcriterionThe transcription has no requirements file: what the published design must do stands in its own documents, not in edakit's form. edakit requires the file before a release (handbook 3.6); it is no point of the design.
checkLIM.hazardous/groundGNDrealR42 (0 Ω) ties GND to the line behind the shunt R41, as the HLW8012 requires: the ESP-12F, the AMS1117 and the headers JP21 and JP22 – the programming port and the external button – sit at mains potential against earth. edakit holds every range against GND, so none of the low-voltage nets reads hazardous; the ESPurna README warns never to connect the board's ground to a computer while it is on mains. Recognised, not checked.
checkLIM.hazardousNEUTRALrealMains neutral against GND – and GND is the line here (R42): the full mains voltage, 358 V peak at 230 V + 10 %. Recognised, not checked, as edakit means it. The board is meant to sit behind a wall switch in the wall box; the ESPurna README warns never to connect the board's ground to a computer and never to flash it while it is on mains.
checkLIM.hazardousNOrealThe load's line at the terminal JP42: at GND (the line) while the relay is on, pulled to neutral through the load while it is off – hazardous voltage, recognised and not checked.
checkLIM.hazardousNCrealAs NO, the other way round: the changeover contact brought out to JP42.2 carries mains whenever the relay leaves it open.
checkLIM.hazardousV2P_D1realThe first tap of the 5 × 470 kΩ divider from neutral to the HLW8012's V2P: four fifths of the mains peak, 286 V. Hazardous voltage on the board, recognised and not checked – its spacing to the low-voltage side is the reviewers'.
checkLIM.hazardousV2P_D2realThe divider's second tap, 215 V peak: hazardous voltage on the board, recognised and not checked.
checkLIM.hazardousV2P_D3realThe divider's third tap, 143 V peak: hazardous voltage on the board, recognised and not checked.
checkLIM.hazardousV2P_D4realThe divider's last tap before V2P, 72 V peak – still above ES1's 60 V. Only V2P itself (0.15 V across R50's 1 kΩ) is below it.
checkLIM.vV11realThe S10K250 across the module's input is rated 250 V AC (VRMS, TDK SIOV StandarD series) – its maximum continuous voltage; 230 V + 10 % (EN 50160) is 253 V rms, and edakit's extremes add the line's volt through the fuses: 254 V. A varistor run above its VRMS leaks more and ages; the 275 V types are the usual ones on 230 V mains, and the ESPurna README's own bill of materials names a 270 V varistor.
checkLVL.undefinedQ4realQ4's gate hangs on GPIO5 alone, without a pull-down: until the firmware drives GPIO5, SEL is undefined and CF1 may give either quantity. Harmless – the firmware sets SEL before it reads CF1 – but the gate floats, unlike Q3's with R32.
checkREQ.missing/leaveGPIO4realThe external button's wire (JP22.3) runs straight into GPIO4 – R22 is a pull-up, not in series; a discharge or a short at the wall switch reaches the ESP's pin.
checkREQ.value/pinIC1.4 (VOUT)realThe AMS1117 datasheet asks for 22 µF (solid tantalum) at the output for stability; the ESPurna-H has 10 µF tantalum (C12) and 100 nF (C21) – 10.1 µF.
simLIM.rangeQ3realGPIO12 drives the relay's 2N7002 through R31/R32 at 3.0 V; its RDS(on) is specified at 5 V and 10 V only, its threshold up to 2.5 V. The model – fitted to the typical part, run at the highest threshold – still pulls the relay in (4.65 V on the coil, 3.75 V needed), but the datasheet does not promise the 71 mA coil current at 3 V: a logic-level MOSFET would.
simLIM.rangeQ4known gapLIM.range/gate (CK-4) finds Q4 half on at VGS 3.3 V. It only pulls SEL low through R49 (0.5 mA): even the part at its highest threshold holds SEL below 1 mV. The rule does not weigh the current, so it warns where nothing burns – as on the SparkFun converter's BSS138.

edakit's false alarms on this design, fixed

  • GND tied to the line by R42 unseen: edakit holds every voltage against the board's ground, so the low-voltage side looked safe. LIM.hazardous/ground names a ground joined to a mains terminal's line or neutral (TD-131).
  • The module's AC input taken as fed by nothing (PATH.unfed on U$1.1, U$1.2): a connector fed a net only with a vbus role, and marking the terminals reversible would have sent PATH.reverse across the mains side. A connector pin of role line or neutral is a supply input now – JP42.3 and JP2 say so (TD-130).
  • The S10K250 (V11) unchecked: edakit had no kind for a varistor, and the transcription entered it as kind ic with behaviour none. The kind varistor holds its VRMS (v_rms_max_v) on AC nets and its VDC (v_max_v) on DC ones – and finds it below 230 V + 10 % (TD-128).
  • The mains held as DC: the KF301 terminals' 300 V AC rating and the HLK-PM01's 85 … 265 V AC input against the 358 V peak, and each divider resistor to the highest voltage of its nets against GND (LIM.v on JP2, JP42, U$1.2, R51 to R53). The mains nets are marked ac now, the AC ratings are v_rms_max_v and hold the rms there, and a resistor between two AC nets sees the difference of their like ends – 72 V peak for each of the five (TD-129).
  • A need on a regulator's VOUT pin left open while its tab, the same terminal, carries the output: taken as not connected (REQ.missing on IC1.2) instead of judged on the output (REQ.value on IC1.4).