edakit documentation

GuitarML Tubescreamer/Rat combo

Why: two drive circuits makers copy often, a Tube Screamer-style and a Rat-style stage, on one board: op-amp stages biased at half the supply, BJT and JFET followers, a 3PDT switch on the board that orders the effects, and footswitches wired by hand. It brings real op-amps where the reference circuit guitar has a test entry, and a reversed electrolytic (C19) that edakit finds.

Keith Bloemer (GuitarML), GuitarPedalPCBs, https://github.com/GuitarML/GuitarPedalPCBs at commit e2fa7e1 (e2fa7e1e22f4939215cfbb1d5a3df2a66068275e, 2026-08-05, "Update README.md"), the pedal TS_Rat_Combo_1590bb ("Custom Tubescreamer/Rat Combo with order switch", the repository's README; the board's silkscreen "Distortion Drive v1.0 9/3/2025 GuitarML"), the schematic TS_Rat_Combo_1590bb/jack_pedal.kicad_sch (KiCad 9), read on 2026-10-31 from a read-only clone (the files' git blob hashes are those of the commit). The netlist was resolved from the schematic (wires, labels, power symbols, the instances of project jack_pedal) by a reader outside this repository and checked against the board file TS_Rat_Combo_1590bb/jack_pedal.kicad_pcb of the same commit, the footprints matched to the symbols by their uuid: all 182 pins of the sheet are on the same nets there (the board's references of the wire pads drop the schematic's numbers – In1 is In, InG3 is OutG, InG5 is InG, both swGnd pads are swGnd). · SVG

Distortion Drive (TS/Rat combo) guitarml-ts-rat-combo · board main graph v1.0 (2026-10-31) · 858 x 524 mm drawn by edakit schematic draw – change the graph, not this drawing U1 TS gain stage U2 Rat gain stage 9v1 9 V in In1 input jack tip InG1 ground of the DC jack InG3 output jack sleeve InG5 input jack sleeve Out1 output jack tip Rat_in1 Rat footswitch: into the Rat Rat_out1 Rat footswitch: out of the Rat Rat_rtn1 TestPoint_THTPad_D2.0mm_Drill1… Rat_send1 TestPoint_THTPad_D2.0mm_Drill… SW_RAT1 Rat LED anode SW_TS1 TS LED anode swGnd1 Rat footswitch LED ground swGnd2 TS footswitch LED ground ts_in1 TS footswitch: into the TS ts_out1 TS footswitch: out of the TS ts_rtn1 TestPoint_THTPad_D2.0mm_Drill1.… ts_send1 TestPoint_THTPad_D2.0mm_Drill1… Other TS_OUT1 TS_OUT1 TS_INN TS_INN TS_INN TS_INN TS_DRIVE TS_DRIVE TS_TONE_P TS_TONE_P TS_C22 TS_INP TS_E1 TS_B1 TS_C5 TS_IN TS_IN TS_TONE_N TS_TONE_N TS_TONE_W TS_C16 TS_OUT2 TS_OUT2 TS_C17 TS_LEVEL TS_C18 TS_B2 TS_E2 TS_C19 TS_OUT TS_OUT RAT_BAL RAT_COMP RAT_COMP RAT_INN RAT_OUT1 RAT_OUT1 RAT_OUT1 RAT_OUT1 RAT_C7 RAT_C8 RAT_INP RAT_C1 RAT_IN RAT_IN RAT_C10 RAT_CLIP RAT_FILT RAT_FILT RAT_TONE RAT_GATE RAT_SRC RAT_VOL RAT_OUT RAT_OUT +9V_IN RAT_LED RAT_LED TS_LED TS_LED IN IN TS_SEND TS_SEND RAT_RTN RAT_RTN RAT_RTN TS_RTN TS_RTN TS_RTN RAT_SEND RAT_SEND OUT OUT VREF VCC VREF VREF VREF VREF VCC VREF VCC VREF VCC VCC VCC VREF VREF VCC VREF 1OUT 1 1IN- 2 1IN+ 3 VCC- 4 VCC+ 8 2OUT 7 2IN- 6 2IN+ 5 U1 TL072 C14 51pF D8 1N914 D9 1N914 POT4 500k R19 1k C22 47nF R29 4.7k R18 51k C13 1uF 3 2 1 Q1 2SC1815 R10 510k R28 1k C5 22nF R9 2.2M R16 10k R17 10k C15 220nF POT5 20k C16 220nF R21 220 R20 10k R22 1k C17 1uF R23 1k POT6 100k C18 100nF 3 2 1 Q2 2SC1815 R25 10k R26 100 + C19 10uF R27 10k R24 510k C3 100nF + C12 47uF BALANCE/COMPENSATION 1 IN- 2 IN+ 3 V- 4 COMPENSATION 8 V+ 7 OUTPUT 6 U2 LM301 C9 30pF C6 100pF POT1 100k R4 47 + C7 2.2uF R5 560 + C8 4.7uF C2 1nF R3 1k C1 22nF R1 1M R2 1M + C10 4.7uF R11 1k D1 1N914 D3 1N914 POT2 100k R12 1.5k C11 3.3nF C20 22nF D 1 S 2 G 3 JN1 2N5458 C21 1uF POT3 100k R14 10k R13 1M Pin_1 1 9v1 TestPoint_THTPad_D2.0mm_Drill1.0mm D2 1N5817 R15 4.7k R6 4.7k Pin_1 1 In1 TestPoint_THTPad_D2.0mm_Drill1.0mm 1 2 3 4 5 9 8 7 6 S1 FS57003PLT2B2M2QE Pin_1 1 InG1 TestPoint_THTPad_D2.0mm_Drill1.0mm Pin_1 1 InG3 TestPoint_THTPad_D2.0mm_Drill1.0mm Pin_1 1 InG5 TestPoint_THTPad_D2.0mm_Drill1.0mm Pin_1 1 Out1 TestPoint_THTPad_D2.0mm_Drill1.0mm Pin_1 1 Rat_in1 TestPoint_THTPad_D2.0mm_Drill1.0mm Pin_1 1 Rat_out1 TestPoint_THTPad_D2.0mm_Drill1.0mm Pin_1 1 Rat_rtn1 TestPoint_THTPad_D2.0mm_Drill1.0mm Pin_1 1 Rat_send1 TestPoint_THTPad_D2.0mm_Drill1.0mm Pin_1 1 SW_RAT1 TestPoint_THTPad_D2.0mm_Drill1.0mm Pin_1 1 SW_TS1 TestPoint_THTPad_D2.0mm_Drill1.0mm Pin_1 1 swGnd1 TestPoint_THTPad_D2.0mm_Drill1.0mm Pin_1 1 swGnd2 TestPoint_THTPad_D2.0mm_Drill1.0mm Pin_1 1 ts_in1 TestPoint_THTPad_D2.0mm_Drill1.0mm Pin_1 1 ts_out1 TestPoint_THTPad_D2.0mm_Drill1.0mm Pin_1 1 ts_rtn1 TestPoint_THTPad_D2.0mm_Drill1.0mm Pin_1 1 ts_send1 TestPoint_THTPad_D2.0mm_Drill1.0mm + C4 47uF R7 10k R8 10k
StageCodeWhereJudgedWhy
checkDOCS.fileedakit.tomlcriterionThe transcription has no requirements file: what the published design must do stands in its own documents, not in edakit's form. edakit requires the file before a release (handbook 3.6); it is no point of the design.
checkPARTS.verified/devicePOT1lacksPOT1, the distortion pot, A100K: the TT Electronics P160 order code that stands in has no LCSC number in the catalogue (the B100K of POT6 has one), and a KiCad design names no EasyEDA device.
checkPARTS.verified/devicePOT2lacksPOT2, the filter pot, A100K: the TT Electronics P160 order code that stands in has no LCSC number in the catalogue (the B100K of POT6 has one), and a KiCad design names no EasyEDA device.
checkPARTS.verified/devicePOT3lacksPOT3, the volume pot, A100K: the TT Electronics P160 order code that stands in has no LCSC number in the catalogue (the B100K of POT6 has one), and a KiCad design names no EasyEDA device.
checkPARTS.verified/devicePOT4lacksPOT4, the drive pot, A500K: the TT Electronics P160 order code that stands in has no LCSC number in the catalogue (the B100K of POT6 has one), and a KiCad design names no EasyEDA device.
checkPARTS.verified/devicePOT5lacksPOT5, the tone pot, W20K (stand-in B20K): the TT Electronics P160 order code that stands in has no LCSC number in the catalogue (the B100K of POT6 has one), and a KiCad design names no EasyEDA device.
checkPARTS.verified/deviceJN1lacksThe 2N5458 of onsemi has no LCSC number (the catalogue lists only Central Semiconductor's, whose data sheet is not reachable from here); a KiCad design names no EasyEDA device.
checkSTRUCT.prefixSW_TS1criterionSW_TS1 is the schematic's own reference of a wire pad (the LED of a footswitch hangs on it); KiCad does not tie references to kinds, edakit reads SW as a switch.
checkSTRUCT.prefixSW_RAT1criterionSW_RAT1 is the schematic's own reference of a wire pad (the LED of a footswitch hangs on it); KiCad does not tie references to kinds, edakit reads SW as a switch.
simLIM.rangeU2realThe LM301A runs from VCC, 8.73 V behind the 1N5817 – below the 10 V (±5 V) from which its data sheet specifies it (SNOSBS0D, note 1 of the electrical characteristics). Rats run on 9 V in practice; the data sheet promises nothing there – offset, swing and common-mode range are unspecified. The TL072 beside it is specified from 4.5 V.
simLIM.vC19realC19 (10 µF electrolytic, the TS output coupling) sits with its plus – pad 1 of the CP_Radial_D5.0mm footprint, the square pad with the '+' – at ts_out, held at 0 V by R27, and its minus at R26 from Q2's emitter, 3.0–3.4 V: reverse-biased in every state. The schematic draws an unpolarized Device:C, the footprint is polarized. Turned round, the finding goes (tests/test_open_designs.py).

edakit's false alarms on this design, fixed

  • The 18 pads for the wires that leave the board – the board's plated pads for a wire or a probe asked for an LCSC part or an EasyEDA device (PARTS.verified/device on each): their entry says own.what "copper" now – the board's own, nothing to buy or pick (TD-127).
  • A base biased by resistors – the TS's 2SC1815 followers through 510 kΩ from the divider node VREF – judged as floating while 'the firmware is not running' (LVL.undefined): only a resistor to the emitter or to a net a pin types counted, not ground and not a divider's middle.
  • A coupling capacitor in a signal path judged from extreme to extreme of its two nets' ranges – C10 and C19, 8.5 V on one side against −4.5 V on the other, 13 V × 1.5 above their 16 V (LIM.v); its two sides carry the same signal, so like ends are compared.
  • Several wires of one net between two boards – the ground to the DC jack, both jack sleeves and both footswitches – stopped the simulation (SIM.converge): the second cable of a net found its ends on different nets.
  • The order switch and the footswitches were never judged by REQ.value/switch: their nets run through cables, and the simulation's per-board node names ('IN__main') were looked up among the signal nets.
  • A switch of three poles could not be described: the roles of the second and third pole were unknown, the simulation switched only the first, and REQ.value/switch took all nine lugs for one contact.